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? freescale semiconductor, inc., 2006, 2007, 20 08, 2009, 2010, 2011. all rights reserved. freescale semiconductor technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. document number: mc1323x rev. 0.0 05/2011 mc1323x package information case 2124-02 lga-48 [7x7 mm] ordering information device device marking package mc13233c 1 1 see table 1 for more details mc13233c lga-48 1 introduction the mc1323x family is freescale?s low cost system-on-chip (soc) platform for the ieee ? 802.15.4 standard that incorporates a complete, low power, 2.4 ghz radio frequency transcei ver with tx/rx switch, an 8-bit hcs08 cpu, and a functional set of mcu peripherals into a 48-pin lga package. this family of products is targeted for wireless rf remote control and other cost-sensitive applic ations ranging from home tv and entertainment systems such as zigbee beestack consumer (rf4ce) to low cost, low power, ieee 802.15.4 and zigbee end nodes. the mc1323x is a highly integrated solution, with very low power consumption. the mc1323x contains an rf transceiver which is an 802.15.4 standard - 2006 compliant radio that operates in the 2.4 ghz ism freque ncy band. the transceiver includes a low noise amplifier, 1mw nominal output power amplifier (pa), inte rnal voltage controlled oscillator (vco), integrated transmit/receive switch, on-board power supply regulation, and full spread-spectrum encoding and decoding. mc1323x low cost soc remote control platform for the 2.4 ghz ieee ? 802.15.4 standard contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 integrated ieee 802.15.4 transceiver (radio and modem) 7 4 hcs08 8-bit central processing unit (cpu) 9 5 system clocks . . . . . . . . . . . . . . . . . . . . . . . 10 6 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 system and power management . . . . . . . . 11 8 mcu peripherals . . . . . . . . . . . . . . . . . . . . . . 12 9 development environment . . . . . . . . . . . . . 16 10pin assignment and connections . . . . . . . 17 11electrical specifications . . . . . . . . . . . . . . . 20 12applications information . . . . . . . . . . . . . . . 32 13mechanical diagrams (case 2124-02, non-jedec) 34
mc1323x advance information, rev. 0.0 2 freescale semiconductor the on-chip cpu is based on the fr eescale hcs08 family of microc ontroller units (mcu) and has 82 kilobyte (kb) of flash memory and 5kb of ram. the onboard mcu peripheral set has been defined to support the targeted applications . a dedicated dma block transfers packet data betw een ram and the transceiver to off-load the cpu and allow higher efficiency and increased performance. 1.1 ordering information table 1 provides additional details about the mc1323x 2features this section provides a simplified bloc k diagram and highlights mc1323x features. 2.1 block diagram figure 1 shows a simplified block diagram of the mc1323x. figure 1. mc1323x simplified block diagram table 1. orderable parts details device operating temp range (ta.) package memory options description mc13233c -40 to 85 c lga-48 5kb ram, 82kb flash intended for smaller memory footprint applications. mc13233cr2 -40 to 85 c lga-48 tape and reel 5kb ram, 82kb flash intended for smaller memory footprint applications. balun switch analog tx analog rx tx modem rx modem digital modem ieee ? 802.15.4 transceiver rf oscillator/pll & clock generation 32 mhz 32.768 khz (optional) clock & reset module (crm) hcs08 core bus interface & memory arbitrator interrupt controller cpu complex 5 kb ram (4 timers, each w/1ch) timer module up to 32 gpio data & address buses debug module 82 kb flash keyboard interface sci/uart interface cmt (ir) module i 2 c module spi interface low battery tx/rx e 12x12 mc1323x analog pwr management & voltage reg advanced security module 802.15.4 phy sequence manager
mc1323x advance information, rev. 0.0 freescale semiconductor 3 2.2 features summary ? fully compliant ieee 802.15.4 standard 2006 transceiver supports 250 kbps o-qpsk data in 5.0 mhz channels and full spread -spectrum encode and decode ? 2.4ghz ? operates on one of 16 selectable channels per ieee 802.15.4 ? programmable output po wer with 0 dbm nominal output power, programmabl e from -30 dbm to +3 dbm typical ? receive sensitivity of - 94 dbm (typical) at 1% per, 20-byte packet, much better than the ieee 802.15.4 standard of -85 dbm ? partial power down (ppd) ?liste n? mode available to reduce curr ent while in receive mode and waiting for an incoming frame ? small rf footprint ? integrated transmit/receive switch ? differential input/output port (typically used with a balun) ? low external component count ? hardware acceleration for ieee ? 802.15.4 applications ? dma interface ? aes-128 security module ? 16-bit random number generator ? 802.15.4 auto-sequence support ? 802.15.4 receiver frame filtering ? 32 mhz crystal reference oscillator; onboard load trim capability supplements external load capacitors ? onboard 1 khz oscillator for wake-up timing or an optional 32.768 khz crystal for accurate low power timing ? transceiver event timer module has 4 timer comparators available to help manage the auto-sequencer and to s upplement mcu tpm resources ? hcs08 8-bit, 32 mhz cpu ? 82 kb (81920 dec) flash memory ? 81920 dec bytes organized as 80 segments by 1024 bytes ? programmable over the full pow er supply range of 1.8 - 3.6 v ? automated program and erase algorithms ? flexible protection scheme to pr event accidental program or erase ? security feature to prevent una uthorized access to the flash ? 5 kb ram ? powerful in-circuit debug and flash progr amming available via on-chip module (bdm) ? two comparator and 9 trigger modes ? eight deep fifo for storing change -of-flow addresses and event-only data
mc1323x advance information, rev. 0.0 4 freescale semiconductor ? tag and force breakpoints ? in-circuit debugging wi th single breakpoint ? multiple low power modes (less than 1 a in stop3) ? keyboard interrupt (kbi) modules ? two keyboard control modules capable of supporting up to a 12x12 keyboard matrix ? 12 dedicated kbi pins support a 6x6 matr ix without impacting other io resources ? 12 kbi interrupts with selectable polarity ? serial communication interface (sci) ? full duplex non-return to zero (nrz) ? baud rates as high as 1 mbps can be supported ? lin master extended break generation ? lin slave extended break detection ? wake-up on active edge ? serial peripheral interface (spi) ? full-duplex or single-wire bidirectional ? double-buffered transmit and receive ? master or slave mode; msb -first or lsb-first shifting ? inter-integrated circ uit (iic) interface - ? up to 100 kbps baud rate with maximum bus loading ? baud rates as high as 800 kbps can be programmed ? multi-master operation ? programmable slave address ? interrupt driven byte-by-byte data transfer; ? supports broadcast mode and 10-bit addressing ? four 16-bit timer/pulse width modulators (tpm[4:1]) - each tpm module has an assigned gpio pin and provides ? single channel capability ? input capture ? output compare ? buffered edge-aligned or center-aligned pwm ? carrier modulator timer (cmt) - ir remote carrier generator, modulator, and transmitter. ? real-time counter (rtc) ? 16-bit modulus counter with bina ry or decimal based prescaler; ? external clock source for precise time base, ti me-of-day, calendar or task scheduling functions ? capable of greater than one day interrupt. ? system protection features ? programmable low voltage wa rning and interrupt (lvi)
mc1323x advance information, rev. 0.0 freescale semiconductor 5 ? optional watchdog timer (cop) ? illegal opcode detection ? 1.8v to 3.6v operating voltage w ith on-chip voltage regulators. ? up to 32 gpio ? hysteresis and selectable pul l-up resistors on all input pins ? configurable slew rate and dr ive strength on all output pins. ? -40c to +85c temperature range ? rohs-compliant 7x7 mm 48-pin lga package 2.3 software solutions freescale provides a powerfu l software environment cal led the freescale beekit wireless connectivity toolkit. beekit is a comprehensive codebase of wireless networking libr aries, application templates, and sample applications. the beekit graphical user interface (gui), part of the beekit wireless connectivity toolkit, allows users to create, modify, and update various wireless networking implementations. a wide range of software functionality is available to complement th e mc1323x and these are provided as codebases within beekit. the following sections describe the available tools. 2.3.1 simple media access controller (smac) the freescale simple media access c ontroller (smac) is a simple ansi c based code stack available as sample source code. the smac can be used for developing proprieta ry rf transceiver applications using the mc1323x. ? supports point-to-point and st ar network configurations ? proprietary networks ? source code and applicat ion examples provided 2.3.2 ieee ? 802.15.4 2006 standard-compliant mac the freescale 802.15.4 standard-compliant mac is a code stack available as object code. the 802.15.4 mac can be used for developing mc1323x networ king applications based on the full ieee ? 802.15.4 standard that use custom networ k layer and application software. ? supports star, mesh and cluster tree topologies ? supports beaconed networks ? supports gts for low latency ? multiple power saving modes ? aes-128 security module ? 802.15.4 sequence support ? 802.15.4 receiver frame filtering.
mc1323x advance information, rev. 0.0 6 freescale semiconductor 2.3.3 synkrorf platform the synkrorf network is a general purpose, proprietary networking laye r that sits on top of the ieee ? 802.15.4 mac and phy layers. it is designed fo r wireless personal area networks (wpans) and conveys information over short distan ces among the participants in the network. it enables small, power efficient, inexpensive solutions to be implemen ted for a wide range of applications. some key characteristics of an synkrorf network are: ? an over-the-air data rate of 250 kbit/s in the 2.4 ghz band. ? 3 independent communication channe ls in the 2.4 ghz band (15, 20, and 25). ? 2 network node types, cont roller and controlled nodes. ? channel agility mechanism. ? low latency tx mode auto matically enabled in conditi ons of radio interference. ? fragmented mode transmission and reception, automatically enabled in conditions of radio interference. ? robustness and ease of use. ? essential functionality to build and support a ce network. the synkrorf network layer uses co mponents from the standard hc(s) 08 freescale platform, which is also used by the freescale?s implementations of 802.15.4. mac and zigbee? laye rs. for more details about the platform components, see the freescale platform reference manual . 2.3.4 beestack consumer freescale?s zigbee rf4ce stac k, called beestack consumer, is a netw orking layer that sits on top of the ieee ? 802.15.4 mac and phy layers. it is designed fo r standards-based wireless personal area networks (wpans) of home entert ainment products and conveys info rmation over shor t distances among the participants in the network. it enables small, power efficient, ine xpensive solutions to be implemented for a wide range of applications. targeted applications include dt v, set top box, a/v receivers, dvd players, security, and other consumer products. some key characteristics of a beestack consumer network are: ? an over-the-air data rate of 250 kbit/s in the 2.4 ghz band ? 3 independent communication channels in the 2.4 ghz band ? 2 network node types, controller node and target node ? channel agility mechanism ? provides robustness and ease of use ? includes essential functionality to build and support a ce network the beestack consumer layer uses components from the standard hcs08 freescale platform, which is also used by the freescal e implementations of 802.15.4. mac or zigb ee? layers. for more details about the platform components, see the freescale platform reference manual .
mc1323x advance information, rev. 0.0 freescale semiconductor 7 2.3.5 zigbee-compliant network stack freescale?s beestack architecture builds on the zi gbee protocol stack. base d on the osi seven-layer model, the zigbee stack ensures inter-operability among networked devices. the physical (phy), media access control (mac), and network (nwk) layers create th e foundation for the application (apl) layers. beestack defines additional services to improve the communication between layers of the protocol stack. at the application layer, the appl ication support layer (asl) facilita tes information exchange between the application support sub- layer (aps) and applicati on objects. finally, zigbee device objects (zdo), in addition to other manufact urer-designed applications, allow for a wide range of useful tasks applicable to home and industrial automation. beestack uses the ieee 802.15.4-complian t mac/phy layer that is not pa rt of zigbee itself. the nwk layer defines routing, network creation and confi guration, and device synchr onization. the application framework (af) supports a ri ch array of services that define zigbee functionality . zigbee device objects (zdo) implement applic ation-level services in all nodes via profiles. a security service provider (ssp) is available to the layers that use encryption (nwk and aps), i.e., advanced encryption standard (aes) 128-bit security. the complete freescale beest ack protocol stack includes the following components: ? zigbee device objects (zdo) a nd zigbee device profile (zdp) ? application support sub-layer (aps) ? application framework (af) ? network (nwk) layer ? security service provider (ssp) ? ieee 802.15.4-compliant mac and physical (phy) layer 3 integrated ieee 802.15.4 transceiver (radio and modem) the mc1323x ieee 802.15.4 fully-compliant transceiver provides a complete 2. 4 ghz radio with 250 kbps offset-quadrature phase shift keying (o-qpsk) data in 5.0 mhz ch annels and full spread-spectrum encode and decode. the modem suppor ts the full requirement of the ieee 802.15.4 standard functionality to transmit, receive, a nd do clear channel assessment (cca), energy detect (ed), and link quality indication (lqi). ? programmable output power with 0 dbm nominal output power, programmable from -30 dbm to +2 dbm typical ? receive sensitivity of -94 dbm (t ypical) at 1% per, 20-byte packet ? differential bi-directio nal rf input/output port ? integrated transm it/receive switch ? receive current can be reduced while waiting or ?listening? for an inco ming frame using partial power down (ppd) mode
mc1323x advance information, rev. 0.0 8 freescale semiconductor 3.1 rf interface and usage the mc1323x rf interface provides a bi-d irectional, differential port that connects dire ctly to a balun. the balun connects directly to a single -ended antenna and converts that in terface to a full differential, bi-directional, on-chip interface wi th transmit/receive switch, lna, and complementary pa outputs.this combination allows for a small f ootprint and low cost rf solution. 3.2 transceiver register interface and operation the transceiver is controlled by set of interface re gisters that are memory-mapped into the cpu address space. the transceiver is capable of independent ope ration to perform transmit, receive, or perform cca/ed operations and combinations. additiona l features of the transceiver include: ? dma function moves data directly between ra m and transceiver buffe rs during transmit and receive on a cycle-steal basis. this off loads th e data transfer from the cpu and provides higher performance. ? interrupt capability dependent on rx packet data availability. an interrupt can be generated based on a programmed count of rx data bytes that have been received a nd moved to ram. this allows cpu filtering of rx data before completion of the packet reception to accelerate response to the packet. ? four transceiver event timer comparators are available to supplement mcu peripheral timer resources for phy and mac timing requirements. 3.3 ieee 802.15.4 acceleration hardware the 802.15.4 transceiver has several hardware features that reduce the software stack size, off load the function from the cpu, and improve performance ? fully supports 2003 & 2006 versi ons of the ieee 802.15 standard. ? supports slotted and unslotted modes ? supports beacon enabled and non-beacon enabled networks ? dma data transfer between ram and radio ? separate aes-128 security module ? 16-bit random number generator ? 802.15.4 sequence support ? rx (conditionally followed by txack) ?tx ? cca (used for cca and ed cycles) ? tx/rx (tx followed by unconditional rx or rcack) ? continuous cca ? 802.15.4 receiver frame filtering.
mc1323x advance information, rev. 0.0 freescale semiconductor 9 3.4 unique partial power down ( ppd) or ?listen? receive mode the mc1323x provides a unique partial power down receive (ppd_rx) mode. when this mode is selected: ? whenever a receive cycle is initia ted, the receiver is not turned fully on to save current until receive energy of a preset level is detected ? the receiver will turn fully on only when triggered by energy at the preset level, and then receives the expected frame. the full-on state is the same as the standard receive state ? the preset level can be programme d for various rx input power levels use of the ppd_rx mode provi des two distinct advantages: 1. reduced ?listen? mode current - the receive curr ent is significantly reduc ed while waiting for a frame. if a node is a coordinator, router, or gate way and it spends a signif icant percentage of its rf-active time waiting for incoming frames from cl ients or other devices, the net power savings can be significant. 2. reduced sensitivity as a desired effect - the pp d_rx mode provides different levels of reduced sensitivity. if a node operates in a densely populat ed area, it may be desi rable to de-sensitize the receiver such that the device does not respond to incoming frames with an energy level below the desired threshold. this could be useful for secu rity, net efficiency, reduc ed noise triggering and many other purposes. 4 hcs08 8-bit central processing unit (cpu) the onboard cpu is a 32 mhz 8-bit hcs08 core. it executes a super set of the 68hc08 instruction set with added bgnd instructions. th e hcs08 cpu is fully source and obj ect code compatible with the m68hc08 cpu. several instructions and enhanced addressing modes are added to improve c compiler efficiency and to support a new ba ckground debug system. it has an 8-bi t data bus, a 16-bit address bus and a 2-stage instruction pi pe that facilitates the ov erlapping of instruction fe tching and execution. there are 29 vectors for internal interrupt sources and one vector for an exte rnal interrupt pi n. the debug or bdm module provides a serial one-wire interface for non-intrusive de bugging of application programs. features of the hcs08 cpu include: ? object code fully upward-compatible with m68hc05 a nd m68hc08 families ? 64-kb cpu address space w ith banked memory management unit for greater than 64 kb ? 16-bit stack pointer (any size stack anywhere in 64-kb cpu address space) ? 16-bit index register (h:x) with powerful indexed addressing modes ? 8-bit accumulator (a) ? many instructions treat x as a second general-purpose 8-bit register ? seven addressing modes: ? inherent ? operands in internal registers ? relative ? 8-bit signed offs et to branch destination ? immediate ? operand in next object code byte(s)
mc1323x advance information, rev. 0.0 10 freescale semiconductor ? direct ? operand in memory at 0x0000?0x00ff ? extended ? operand anywhere in 64-kb address space ? indexed relative to h:x ? five submodes including auto increment ? indexed relative to sp ? impr oves c efficiency dramatically ? memory-to-memory data move instructions with four address mode combinations ? overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ? efficient bit manipulation instructions ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? stop and wait instructions to invoke low-power operating modes 5 system clocks the primary system reference freque ncy is a 32 mhz crystal oscillator . the crystal requirements for the oscillator and oscillator performa nce must support a +/-40 ppm freque ncy accuracy to meet the ieee 802.15.4 standard requirements. all syst em clocks are generated from this source. features of the clock system include: ? the 32 mhz reference oscillator has onboard programmable capacitive loading that allows software tuning of frequency accuracy ? cpu clock as high as 32 mhz ? bus clock (and peripheral cl ock) equals 1/2 cpu clock ? clocks to individual peripherals can be indepe ndently disabled for be st power management. ? cpu clock can be lowered to 500 khz for lower power (250 khz bus clock) an optional 32.768 khz crystal oscillator is available for accurate low power ti ming and the real time clock (rtc). also, an onboard, low accuracy 1 khz oscillator is available for sleep timing wake-up. 6memory the mc1323x memory resources consist of ram, fl ash program memory for nonvolatile data storage, and control/status registers for i/ o, peripherals, management, and th e transceiver. features include: ? 80 kb flash (81920 dec ) bytes organized as 80 segments of 1024 byte/segment) ? 5 kb ram ? security circuitry to prevent unauthor ized access to ram and flash contents
mc1323x advance information, rev. 0.0 freescale semiconductor 11 7 system and power management the mc1323x is inherently a low pow er device, but it also has extensive system control and power management to maximize battery li fe and provide system protection. 7.1 modes of operation the mc1323x modes of operation include: ? active background mode for code development ? run mode ? cpu clocks can be run at full sp eed and the internal supply is fully regulated. ? lprun mode ? cpu clock is set to 500 khz and peripheral clocks (bus clock) to 250 khz and the internal voltage regul ator is in standby ? wait mode ? cpu shuts down to conserve power ; system clocks are r unning and full regulation is maintained ? lpwait mode ? cpu shuts down to conserve power; peripheral cloc ks are restricted to 250 khz and the internal voltage regulator is in standby ? stop modes ? system clocks are stopped and voltage regulator is in standby ? stop3 ? all internal circuits are powered for fast recovery (32 mhz oscillator on-off optional) ? stop2 ? partial power down of internal circuits , ram content is retained; i/o states are held 7.2 power management the mc1323x power management is controlled th rough programming of th e modes of operation. different modes allow for different levels of power-down. additiona l features include: ? the transceiver is powered as required ? the analog radio is only powered-up as re quired to do a tx, rx, or cca/ed operation ? peripheral control clock gating can be disabl ed on an mcu module-by-module basis to provide lowest power ? programmed mode manages ? degree of chip power down ? retention of programmed parameters ? clock management ? power-down and wake-up (clocks and anal og blocks) are gracefully controlled ? rtc can be used as wake-up timer ? wake-up available through kbi and uart rx asynchronous interrupts ? real-time counter (rtc) module ? 16-bit modulus counter with binary or deci mal based prescaler for precise time base, time-of-day, calendar or task scheduling functions. ? capable of greater than one day interrupt. ? can also be used for device wake-up.
mc1323x advance information, rev. 0.0 12 freescale semiconductor 7.3 system protection the mc1323x provides several vehicles to maintain security or a high level of system robustness: ? watchdog computer operating prope rly (cop) reset with option to run from dedicated internal clock source or bus clock ? low-voltage warning and det ection with reset or interr upt; selectable trip points ? illegal opcode detection with reset ? flash block protection 8 mcu peripherals the mc1323x has a functional se t of mcu peripherals focuse d for intended applications. 8.1 parallel input/output (gpio) the mc1323x has four i/o ports th at provide up to 31 general-pur pose i/o signals and 1 output only signal. many of these pins are shared with on-chip peripherals such as timer systems, communication ports, or keyboard interrupts. when these other modules are not controlling the por t pins, they revert to general-purpose i/o control. for each i/o pin, a port data bit provides access to input (read) and output (write) data, a data directi on bit controls the direction of the pin, and a pullup enab le bit enables an internal pullup device (provided the pin is configured as an input ), and a slew rate control bit controls the rise and fall times of the pins.par allel i/o features include parallel i/o features include: ? a total of 32 general-purpose i/o pins in four ports (pta2 is output only) ? hysteresis input buffers ? software-controlled pu ll-ups on each input pin ? software-controlled sl ew rate output buffers ? eight port a pins shared with 32 .768 khz oscillator, irq, iic, and bkgd ? eight port b pins shared with kbi1[7:0] ? eight port c pins shared with kbi2[3:0] and spi ? eight port d pins shared wi th tpm0, tpm1, tpm2, tpm3, cm t (with 20ma drive), uart, and 32mout (reference fr equency clock output) 8.2 keyboard interrupt modules (kbi) the mc1323x has two kbi modules; kbi1 shares eight port a pins and kb i2 shares the lower four pins of port c. any kbi pin can be enabled as a keyboard i nput that can act as an interrupt request. as a result, the total 12 kbi inputs allows as la rge as a 12x12 keyboard ma trix with use of othe r gpio pins as outputs to the matrix. all enabled kbi inputs can be configur ed for edge-only sensitivity or edge -and-level sensitivity. they also can be configured for either rising edge / high-level or falling-edge/l ow-level sensitivity. when enabled
mc1323x advance information, rev. 0.0 freescale semiconductor 13 for rising edge / high level sensitivit y, a pulldown resistor is enabled, a nd when enabled for falling edge / low level sensitivity, a pull-up resistor is enabled. the kbi features include: ? kbi1 has eight keyboard interrupt pins with individual pin enable bits. ? kbi2 has four keyboard interrupt pins with individual pin enable bits. ? supports up to a 12x12 keyboard matr ix. a 6x6 matrix can be suppor ted without impacting other i/o functions. ? each keyboard interrupt pin is pr ogrammable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sens itivity. pull-ups and pull-downs enabled by selected mode. ? individual signal software enabled interrupts for both kbi1 and kbi2. ? can be used for device wake-up 8.3 serial communications interface (sci) module the mc1323x has one serial communications interf ace module ? sometime s called a universal asynchronous receiver/tran smitter (uart). typically, th is port is used to co nnect to the rs232 serial input/output (i/o) port of a personal computer or workst ation, and it can also be us ed to communicate with other embedded controllers. the sci module has a single, flexible frac-n (13-bi t modulo counter, 5-bit fract ional counter) baud rate generator used both for transmit and receive. wi th a maximum 16 mhz periphe ral clock, baud rates as high as 1 mbps can be supported (standard is 921,600 baud). this sci system offers many adva nced features not commonly found on other asynchronous serial i/o peripherals on other embedded cont rollers. the receiver employs an advanced data sampling technique that ensures reliable communicati on and noise detection. hardware parity, receiver wake-up, and double buffering on transmit and r eceive are also included. features of sci module include: ? full-duplex, standard non-re turn-to-zero (nrz) format ? double-buffered transmitter and re ceiver with separate enables ? programmable high accuracy ba ud rates (frac-n generator) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full ? receive overrun, parity error, framing erro r, and noise error ? idle receiver detect ? active edge on receive pin ? break detect supporting lin ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length
mc1323x advance information, rev. 0.0 14 freescale semiconductor ? receiver wake-up by idle -line or address-mark ? optional 13-bit break character generati on / 11-bit break character detection ? selectable transmitt er output polarity 8.4 serial peripheral interface (spi) module the mc1323x has one serial periphe ral interface module. the spi is a synchronous serial data input/output port used for interfaci ng with serial memories, peripheral devices, or other processors. the spi allows an 8-bit serial bit stream to be shifted simultaneous ly into and out of the device at a programmed bit-transfer rate (calle d 4-wire mode). there are four pi ns associated with the spi port (spclk, mosi, miso, and ss). the spi module can be programmed for master or slav e operation. it also supports a 3-wire mode where for master mode the mosi becomes momi, a bidire ctional data pin, and fo r slave mode the miso becomes siso, a bidirec tional data pin. in 3-wire mode, data is onl y transferred in one direction at a time. the spi bit clock is derived from the periphera l input clock with a maximum 16 mhz operation. a programmable prescaler (m aximum divide-by-8) drives a se cond baud rate programmable divider (maximum divide-by-256) to develop the bit cl ock. the maximum spi transfer rate is 8 mhz. features of spi module include: ? master or slave mode operation ? full-duplex or single-w ire bidirectional option ? 8-bit only transfer size ? programmable transmit bit rate (8 mhz max) ? double-buffered transmit and receive ? serial clock phase and polarity options (supports all 4 options) ? optional slave select output ? selectable msb-first or lsb-first shifting 8.5 inter-integrated circuit (iic) interface module the mc1323x has one inter-integrated circuit interf ace module that provides a method of communication between a number of other integrated circuits. the ii c bus interface provides a bi directional, 2-pin (sda bus data and scl bus clock) serial bus designed to operate up to 100 kbps with maximum bus loading and timing. the module is capable of ope rating at higher baud rates, up to a maximum of peripheral clock/20 (800 kbps), with reduced bus loading. features of iic module include: ? compatible with iic bus standard ? multi-master operation ? software programmable clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer
mc1323x advance information, rev. 0.0 freescale semiconductor 15 ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection ? general call recognition ? 10-bit address extension 8.6 timer/pwm (tpm) modules the mc1323x has four independent timer/pwm modules, each with one channel. each tpm module is based on a 16-bit counter and provides input capture, output compare, and pulse width modulation. each tpm module has one associated i/o pin fo r input capture or counter/pwm output. tpm module features include: ? each tpm may be configured for buffered, cente r-aligned pulse-width modulation (cpwm) on all channels ? module clock source is pe ripheral clock or reference oscillator divided-by-1024 ? clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 ? 16-bit free-running or up/ down (cpwm) count operation ? 16-bit modulus register to control counter range ? module enable ? one interrupt per channel plus a termin al count interrupt for each tpm module ? channel features: ? each channel may be input capture, output compare, or buffered edge-aligned pwm ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? selectable polarity on pwm outputs 8.7 carrier modulator timer (cmt) module the mc1323x carrier modulator timer module is intended as an ir led driver for remote control ?blaster? applications. the module consists of a carrier genera tor, modulator, and transmitte r that drives data to the output (iro) pin either in baseband or in fsk mode. the iro pin drives (modulates) the ir diode directly or through a buffer depending on the required curren t. the iro pin is specified for 20ma drive. the cmt module features include: ? four modes of operation ? time with independent cont rol of high and low times ? baseband
mc1323x advance information, rev. 0.0 16 freescale semiconductor ? frequency shift key (fsk) ? direct software c ontrol of iro pin ? extended space operation in ti me, baseband, and fsk modes ? module clock source is pe ripheral clock (16 mhz max) ? interrupt on end of cycle ? ability to disable iro pin and use as timer interrupt 8.8 real-time counter (rtc) module the mc1323x real-time counter module consists of one 16-bit counter, one 16-bit comparator, several binary-based and decimal-based pr escaler dividers, three clock sour ces, and one programmable periodic interrupt. this module can be used for time-of-day, calendar or any task scheduling functions. it can also serve as a cyclic wake-up from low power modes (stop2, stop3 and wait). rtc can be clocked from bus clock, the optional 32.768 khz oscillator or the onboard 1 khz low power oscillator. features of the rtc module include: ? 16-bit up-counter ? 16-bit modulo match limit ? software controllable periodic interrupt on match ? three software selectable clock sources for input to prescaler with progr ammable 16 bit prescaler ? 32.768 khz optional crystal oscillator. ? 32 mhz reference oscillator ? 1 khz low power rc oscillator ? useful for time base tick or time-of-day clock ? can be used for device wake-up; capable of greater than one day time-out period. 9 development environment development support for the hcs08 on the mc132 3x includes the background debug controller (bdc) and the on-chip debug module (dbg). the bdc provi des a single-wire (signal bkgd) debug interface to the mcu that provides a conveni ent interface for programming the on- chip flash and other storage. the bdc is also the prim ary debug interface for development and al lows non-intrusive access to memory data and traditional debug features such as cpu register modify, brea kpoints, and single instruction trace commands. address and data bus signals are not available on external pins. debug is done through commands fed into the mcu via the single-wire background debug in terface. the debug module provides a means to selectively trigger and capture bus information so an external devel opment system can reconstruct what happened inside the mcu on a cycle-by -cycle basis without ha ving external access to the address and data signals. features include: ? single-wire background debug interface
mc1323x advance information, rev. 0.0 freescale semiconductor 17 ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) ? on-chip in-circuit emulator (ice) debug module containing three comparat ors and nine trigger modes. ? eight deep fifo for storing change-of-flo w addresses and event-only data. debug module supports both tag and force breakpoints. 10 pin assignment and connections 10.1 device pin assignment figure 2. mc1323x pinout
mc1323x advance information, rev. 0.0 18 freescale semiconductor 10.2 pin definitions table 2 details the mc1323x pinout and functionality. table 2. pin function description pin # pin name type description functionality 1 pta0/xtal_32k digital input/output port a bit 2 / 32.768 khz oscillator output 2 pta1/extal_32 k digital input/output port a bit 3 / 32.768 khz o scillator input for normal use, 10kohm resistor to ground recommended 3 reset digital input/output device asynchronous hardware reset. active low. onboard pullup normally input; gets driven low for a period after a reset 4 pta2 digital output port a bit 2 / test mode enable. tm mode input. must be biased low exiting por for normal operation 5 pta3/irq digital input/output port a bit 3 / irq. 6pta4/ xtal_32kout digital input/output port a bit 4 / buffered 32.768 khz clock output optional 32.768 khz output clock for measuring reference oscillator accuracy (ppm) 7 pta5/sda digital input/output port a bit 5 / iic bus data defaults to open drain for iic 8 pta6/scl digital input/output port a bit 6 / iic bus clock defaults to open drain for iic 9 pta7/bkgd/ms digital input/output port a bit 7 / background / mode select debug port signal 10 ptb0/kbi1p0 digital input/output port b bi t 0 / kbi1 input bit 0 wake-up capability 11 ptb1/kbi1p1 digital input/output port b bi t 1 / kbi1 input bit 1 wake-up capability 12 ptb2/kbi1p2 digital input/output port b bi t 2 / kbi1 input bit 2 wake-up capability 13 ptb3/kbi1p3 digital input/output port b bi t 3 / kbi1 input bit 3 wake-up capability 14 ptb4/kbi1p4 digital input/output port b bi t 4 / kbi1 input bit 4 wake-up capability 15 ptb5/kbi1p5 digital input/output port b bi t 5 / kbi1 input bit 5 wake-up capability 16 ptb6/kbi1p6 digital input/output port b bi t 6 / kbi1 input bit 6 wake-up capability 17 ptb7/kbi1p7 digital input/output port b bi t 7 / kbi1 input bit 7 wake-up capability 18 ptc0/kbi2p0 digital input/output port c bi t 0 / kbi2 input bit 0 wake-up capability 19 vbatt_4 power input vdd supply input 1 connect to system vdd supply 20 ptc1/kbi2p1 digital input/output port c bi t 1 / kbi2 input bit 1 wake-up capability 21 ptc2/kbi2p2 digital input/output port c bi t 2 / kbi2 input bit 2 wake-up capability 22 ptc3/kbi2p3 digital input/output port c bi t 3 / kbi2 input bit 3 wake-up capability 23 ptc4/spiclk digital input/output port c bit 4 / spi clock 24 ptc5/ss digital input/output port c bit 5 / spi slave select 25 ptc6/miso digital input/output port c bit 6 / spi miso 26 ptc7/mosi digital input/output port c bit 7 / spi mosi
mc1323x advance information, rev. 0.0 freescale semiconductor 19 27 ptd0/tpm0 digital input/output port d bit 0 / tpm0 signal tpm1 timer output / gate input signal 28 ptd1/tpm1 digital input/output port d bit 1/ tpm1 signal tpm2 timer output / gate input signal 29 ptd2/tpm2 digital input/output port d bit 2 / tpm2 signal tpm3 timer output / gate input signal 30 ptd3/tpm3 digital input/output port d bit 3 / tpm3 signal tpm4 timer output / gate input signal 31 ptd4/cmt digital input/output port d bit 4/ cmt output hi drive output for ir diode 32 ptd5/txd digital input/output port d bit 5 / uart txd output uart has no hardware flow control 33 ptd6/rxd digital input/output port d bit 6 / uart rxd input uart has no hardware flow control 34 ptd7 digital input/output port d bit 7 35 xtal_32m analog output 32 mhz reference oscillator output 36 extal_32m analog input 32 mhz reference oscillator input 37 vbatt_3 power input vdd supply input 1 connect to system vdd supply 38 vreg_vco vco reg out / in vco regulator output and input to vco 1.8 vdc vdd bypass to ground with 220 nf capacitor. 39 vdd_ana analog power input analog 1.8 vdc input connect to vreg_ana 40 nc no connect 41 rf_n rf input/output modem rf input/output negative bi-directional rf port for the internal lna and pa 42 rf_p rf input/output modem rf input/output negative bi-directional rf port for the internal lna and pa 43 rf_bias rf voltage output switched rf bias voltage (1.8 vdc) high for tx; low for rx 44 vbatt_2 power input vdd supply input 1 connect to system vdd supply 45 nc input no connect connect to ground 46 vreg_lo2 lo2 reg out lo2 regulator output @ 1.8 vdc bypass to ground with 220 nf capacitor. 47 vreg_ana ana reg out analog regulator output @ 1.8 vdc bypass to ground with 220 nf capacitor. connect to vdd_ana 48 vbatt_1 power input vdd supply to analog regulator 1 connect to system vdd supply flag gnd power input system ground 1 vbatt_1, vbatt_2, vbatt_3 and vbatt_4 signals are not connected onboard mc1323x. table 2. pin function description (continued) pin # pin name type description functionality
mc1323x advance information, rev. 0.0 20 freescale semiconductor 11 electrical specifications this section details maximum rati ngs for the 48-pin lga package, recommended operating conditions, dc characteristics, and ac characteristics. 11.1 package maximum ratings absolute maximum ratings are stress ratings only, and functional opera tion at the maximu m rating is not guaranteed. stress beyond th e limits specified in table 3 may affect device reliability or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v batt ) or the programmable pull-up resistor associated w ith the pin is enabled. table 3 shows the maximum ratings for the 48-pin lga package. 11.2 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling preca utions should be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. all esd testing is in conformity with the jesd22 stress test qualificati on for commercial grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). all latchup test testing is in conformity with the jesd78 ic latch-up test. table 3. lga package maximum ratings rating symbol value unit maximum junction temperature t j 125 c storage temperature range t stg 125 c moisture sensitivity level msl3-260 reflow soldering temperature 260 c power supply voltage v batt -0.3 to 3.7 vdc digital input voltage vin -0.3 to (v dd + 0.3) vdc rf input power p max 10 dbm note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to th e limits in the electrical characteristics or recommended operating conditions tables. note: all pins meets esd human body model (hbm) = 2 kv
mc1323x advance information, rev. 0.0 freescale semiconductor 21 a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. 11.3 recommended op erating conditions note the mc13233 transceiver provides an ieee ? 802.15.4 standard phy compliant node over all reco mmended operating conditions. table 4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin 1 1 this number represents a minimum number for both positive pulse(s) and negative pulse(s) ?1 machine series resistance r1 0 storage capacitance c 200 pf number of pulses per pin 1 ?1 latch-up minimum input voltage limit ? 1.8 v maximum input voltage limit 4.32 v table 5. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 machine model (mm) v mm 200 ? v 3 charge device model (cdm) v cdm 750 ? v 4 latch-up current at t a = 85 ci lat 100 ? ma table 6. recommended operating conditions characteristic symbol min typ max unit power supply voltage (v batt )v batt 1.8 1 2.7 3.6 vdc input frequency f in 2.405 - 2.480 ghz operating temperature range t a -40 25 85 c logic input voltage low v il 0 - 30% v batt v logic input voltage high v ih 70% v batt -v batt v
mc1323x advance information, rev. 0.0 22 freescale semiconductor 11.4 dc electrical characteristics output load current (with specified v olmax and v ohmin ) all standard gpio cmt output iro i o - - - - 3 20 ma rf input power p max --10dbm crystal reference oscillator frequency (40 ppm over operating conditions to meet the 802.15.4 standard.) f ref 32 mhz only 1 although the device functions at v dd min, the supply must first rise above v lvdl . as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above v lvdl . table 7. dc electrical characteristics (vbatt = 2.7 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit power supply voltage (voltage applied to power input pins; vbatt_1, vbatt_2, vbatt_3, and vbatt_4) v dd 1.8 1 2.7 3.6 vdc minimum cpu run voltage (radio and peripherals not guaranteed operational; cpu, ram, and flash operational) v dd_run 1.6 vdc minimum ram retention voltage (voltage applied to vbatt power input pins) v ram v por vdc low-voltage detection threshold - high range (all conditions 2 ) v dd falling v dd rising v lvdh 2.18 2.20 2.23 2.26 2.32 2.32 vdc low-voltage detection threshold - low range (all conditions) v dd falling v dd rising v lvdl 1.67 1.68 1.70 1.77 1.80 1.96 vdc low-voltage warning threshold - high range (all conditions) v dd falling v dd rising v lvwh 2.25 2.30 2.32 2.36 2.45 2.42 vdc low-voltage warning threshold - low range (all conditions) v dd falling v dd rising v lvwl 1.79 1.74 1.81 1.84 1.91 1.99 vdc power-on reset (por) voltage vpor - 1.0 - vdc high impedance (off-state) leakage current (per pin) ( v in = v dd or v ss , all input/outputs, device must not be in low power mode) |i oz |- -1.0 a input current (v in = 0 v or v ddint ) ( v in = v dd or v ss , all input/outputs, device must not be in low power mode) i in --1.0a input low voltage (all digital inputs) v il 0-30% v batt v input high voltage (all digital inputs) v ih 70% v batt -v batt v table 6. recommended operating conditions (continued) characteristic symbol min typ max unit
mc1323x advance information, rev. 0.0 freescale semiconductor 23 11.5 supply current characteristics input hysteresis (all digital inputs) v hys 0.06 v dd ? v internal pullup resistors 3 (all port pins and irq except cmt) r pu -20- kohm internal cmt pullup resistor 3 r pu - 10 - kohm internal pulldown resistors 3 (kbi pins and irq) r pd -20- kohm output high voltage all standard gpio = 3ma cmt output iro = 20 ma v oh 80% v batt -v batt v output low voltage (all digital outputs) all standard gpio = 3ma cmt output iro = 20 ma v ol 0-20% v batt v input capacitance (all non-supply pins) c in ?3?pf 1 although the device functions at v dd min, the supply must first rise about v lvdl . as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above v lvdl . 2 denotes full voltage supply and temperature ranges. 3 measurement condition for pull resistors: v in = v ss for pullup and v in = v dd for pulldown. table 8. supply current characteristics (vbatt = 2.7 v, t a = 25 c, unless otherwise noted) characteristics symbol min typ max unit stop2 ? all internal circuitry off, ram retained , reference oscillator off, kbi active. i/o values are latched to preserve state. rtc off. rf in reset. ? all internal circuitry off, ram retained , reference oscillator off, kbi active. i/o values are latched to preserve state. rtc on with 1 khz osc. rf in reset. ? all internal circuitry off, ram retained , reference oscillator off, kbi active. i/o values are latched to preserve state. rtc on with 32.768 khz osc. rf in reset. s2i dd 0.29 0.40 0.40 1 1 3 a stop3 ? all internal circuitry off, ram, i/o, internal registers & selectable peripheral registers retained, 32mhz ref oscillator off, rtc off, lvd off. rf in reset. ? all internal circuitry off, ram, i/o, internal registers & selectable peripheral registers retained, 32mhz ref oscillator off, rtc on with 1 khz osc, lvd off. rf in reset. ? all internal circuitry off, ram, i/o, internal registers & selectable peripheral registers retained, 32mhz ref oscillator off, rtc on with 32.768 khz osc, lvd off. rf in reset. ? all internal circuitry off, ram, i/o, internal registers & selectable peripheral registers retained, 32mhz ref oscillator on, rtc on with 32 mhz osc, lvd off. rf in reset s3i dd 0.45 0.55 2.65 330 a table 7. dc electrical characteristics (continued) (vbatt = 2.7 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit
mc1323x advance information, rev. 0.0 24 freescale semiconductor lpwait low power wait ? entered from lprun ? processor off, bus clock @ 250 khz, voltage regulator is standby. ? peripherals and modem clocks disabled. rf in reset. lpwi dd 0.50 0.56 0.62 ma lprun low power run ? processor forced to 500 khz and bus clock@ 250 khz ? peripheral state & ram retained. voltage regulators in standby. ? peripherals and modem clocks disabled. rf in reset. lpri dd 0.53 0.76 0.85 ma run ? processor running at 32 mhz and peripheral clock @ 16 mhz ? all peripheral clocks disabled 1 & ram active, voltage regulators fully on. ? rf in reset. runi dd 4.0 4.7 4.9 ma tx ? mcu in lprun (peripheral clock @ 250 khz) ? rf in transmit mode (nominal power out) 2 txi dd 21.3 26.6 28.2 ma rx_ppd ? mcu in lprun (peripheral clock @ 250 khz) ? rf in receive partial power down mode rxppdi dd 22.3 ma rx ? mcu in lprun (peripheral clock @ 250 khz) ? rf in receive mode either 1) waiting @ full sensitivity or 2) receiving actual frame rxi dd 26.8 34.2 35.0 ma 1 registers scgc1 and scgc2 = 0x00 2 tx output power set to nominal (0 dbm). table 9. typical current adders for enabled functions (32mhz cpu clock) (vbatt = 2.7 v, t a = 25 c, unless otherwise noted) parameter description typical current unit tpm tpm module enabled (each) 90 a kbi kbi enabled 25 a iic iic enabled 175 a sci sci enabled 150 a spi spi enabled 70 a cmt cmt enabled 78 a irq irq clock enabled 23 a debug debug module clock enabled 135 a modem modem (transceiver) clock enabled 285 a aes aes clock enabled 65 a table 8. supply current characteristics (continued) (vbatt = 2.7 v, t a = 25 c, unless otherwise noted) characteristics symbol min typ max unit
mc1323x advance information, rev. 0.0 freescale semiconductor 25 figure 3. typical run current versus cpu clock (only 0.5, 1, 2, 4, 8, 16, and 32 mhz available) 11.6 rf ac electrical characteristics note all specified rf parameters are referenced to the package pins and are the result of measurements in th e reference circuit shown in figure 5 . table 10. receiver ac electrical charac teristics for 802.15.4 modulation mode (vbatt = 2.7 v, ta = 25 c, f ref = 32mhz, unless otherwise noted.) characteristic symbol min typ max unit sensitivity for 1% packet error rate (per) (+25 c, @ package interface) 1 1 measured at f c = 2450 mhz; see figure 4 for rx performance vs. channel frequency sens 25 c -94 -91 dbm sensitivity for 1% pa cket error rate (per ) (over all conditions) 2 2 all conditions includes -40c to +85c, vbatt = 1.8v to 3.6v, and full frequency range sens -89 dbm saturation (maximum input level) sens max 10 dbm channel rejection for 1% per +5 mhz (adjacent channel) 3 -5 mhz (adjacent channel) 3 +10 mhz (alternate channel) 4 -10 mhz (alternate channel) 4 >= 15 mhz 5 3 ieee 802.15.4 standard specifies minimu m adjacent channel rejection as 0 db 4 ieee 802.15.4 standard specifies minimu m alternate channel rejection as 30 db 5 this parameter represents an average of all readings across all channels 39 35 46 46 53 db frequency error tolerance 6 6 minimum set by ieee 802.15.4 standard 200 - - khz symbol rate error tolerance 6 80 - - ppm
mc1323x advance information, rev. 0.0 26 freescale semiconductor figure 4. typical rx sensitivit y vs. channel frequency @ 25c table 11. transmitter ac electrical char acteristics for 802.15.4 modulation mode (vbatt = 2.7 v, t a = 25 c, f ref = 32 mhz, unless otherwise noted.) characteristic symbol min typ max unit nominal output power 1 1 register sets output power to nominal (0 dbm). p out -2.5 0 2.3 dbm maximum output power 2 2 register sets output power to maximum. -+2- dbm error vector magnitude evm <16 18 % output power control range - 30 - db over the air data rate - 250 - kbps 2nd harmonic 3 3 measurements taken at output of evaluation circuit set for maximum power out and averaged over 100ms. --44 4 4 with use of external filtering / harmonic trap as implemented in reference circuit. - dbm/(100 khz) 3rd harmonic and greater 3 --54 4 - dbm/(100khz) spurious emissions 5 <1 ghz (quasi-peak detection mode) >1 ghz (peak detection mode) lower band edge (peak detection mode) upper band edge (peak detection mode) 5 derived from measured radiated values in units of dbuv/m and converted to eirp (dbm). -66 -40 -34 -23 dbm dbm/mhz dbm/mhz dbm/mhz
mc1323x advance information, rev. 0.0 freescale semiconductor 27 figure 5. rf parameter reference circuit 11.7 crystal reference clock oscillator characteristics the reference oscillator model includ ing external crystal in shown in figure 6 . the ieee 802.15.4 standard requires a frequency tolera nce less than or equal to +/- 40 ppm as shown in the oscillator specification table 12 . with a suitable crystal (refer to table 13 ), the device frequency tolerance can typically trimmed to be held to +/- 30 ppm over all conditions. figure 6. 32mhz refere nce oscillator model c6 10 pf l2 0.0039uh 1 2 c7 1pf c2 10 pf rf_50 z_rf_n rf _p j1 sma 1 g1 g3 g2 g4 rf _n harmonic trap z_rf_p rf_bias u2 mc1323x rf _p 42 rf _n 41 nc/tinj_n 45 rf_bias/tinj_p 43 rf _bias l1 0. 00 33 uh 1 2 z1 50/100 oh ms 5 1 6 2 3 4 c17 10pf dnp ? y1 crystal cstray reference oscillator 32 mhz extal_32m xtal_32m 0-300 ff with steps of 20 ff. cstray fine tune [3:0] fine tune [3:0] mc1323x 0-4.215 pf with steps of 281 ff. coarse tune [3:0] coarse tune [3:0] cl1 cl2 0-300 ff with steps of 20 ff. 0-4.215 pf with steps of 281 ff.
mc1323x advance information, rev. 0.0 28 freescale semiconductor 11.8 optional 32.768 khz crystal oscillator specifications figure 7. 32.768 khz oscillator mode table 12. reference oscillator specifications characteristic symbol min typ max unit frequency (nominal) 32.000000 mhz oscillator frequency tolerance over temperature range. +/- 30 +/- 40 ppm external load capacitance c lext 8pf internal osc startup time 1 1 this is part of device wake-up time. t cst 800 s table 13. recommended 32 mhz crystal specifications parameter value unit condition frequency 32.000000 mhz frequency tolerance (cut tolerance) 10 ppm max at 25 c frequency stability (temperature drift) 16-18 ppm over desired temperature range aging 2 ppm max equivalent series resistance 60 max load capacitance 9 pf shunt capacitance <2 pf max mode of oscillation fundamental ? y1 crystal cstray 1 32.768 khz oscillator xtal_32k extal_32k cstray 2 cl2 cl1 rf
mc1323x advance information, rev. 0.0 freescale semiconductor 29 l 11.9 internal low speed reference oscillator specifications 11.10 control timing and cpu bus specifications table 14. 32.768 oscillator cr ystal typical specifications characteristic symbol min typ max unit crystal frequency 32.768 khz frequency tolerance @ 25 c 20 ppm load capacitance 12 12.5 16 pf equivalent series resistance (esr) 40 130 k shunt capacitance 2 pf tolerated drive level 1 w table 15. internal 1 khz oscillator specifications characteristic symbol min typ max unit default frequency @ 25 c 0.80 1.0 1.40 khz oscillator frequency variation over temperature 1 deviation at -40 c from 25 c frequency deviation at +85 c from 25 c frequency 1 this percentage deviation is typical change from t he individual device oscillator frequency at 25 c - -13 +6 - % table 16. mcu control timing (vbatt = 2.7 v, t a = 25 c, f ref = 32mhz, unless otherwise noted.) parameter symbol min typical max unit cpu frequency (t cyc = 1/rdiv) f cpu f ref /64 1 1 the 32mhz reference clock. ?32 1 mhz bus frequency (always 1/2 cpu clock) (t cyc = f bus) f bus f cpu /2 mhz external reset pulse width 100 ? ? ns external asynchronous minimum interrupt pulse width (kbi or irq) 2 2 minimum pulse to recognize a asynchronous transition 100 ? ? ns external synchronous minimum interrupt pulse width (kbi or irq) 3 4 3 minimum pulse to recognize a level sensitive 4 for determination of an actual key/push bu tton in a matrix, this pulse with must rema in present for the keyboard scan routine duration. thus, the minimum pulse width would be dete rmined by the software, not the detection hardware. 1.5 t cyc ??ns wake-up time from stop2 or stop3 800 s
mc1323x advance information, rev. 0.0 30 freescale semiconductor 11.11 spi timing figure 8. spi timing diagram table 17 describes the timing require ments for the spi system. table 17. spi timing parameter symbol min typical max unit master spi_sck period t cyc bus_clk*2 38 bus_clk *256 ns slave spi_sck period t cyc 10 ns slave spi_ss setup time t ss_su 10 ns slave spi_ss hold time t ss_h 10 ns slave spi_mosi setup time t si_su 10 ns slave spi_mosi hold time t si_h 10 ns master spi_miso setup time t mi_su 20 ns master spi_miso hold time t mi_h 0ns master spi_mosi output time t mo 5ns slave spi_miso output time (with 15 pf load) t so 20 ns spi_sck spi_mosi (slave in) spi_ss (slave in) spi_miso (master in) t xx_su t xx_h t cyc t ss_su t ss_h t mo, t so spi_mosi (master out) spi_miso (slave out)
mc1323x advance information, rev. 0.0 freescale semiconductor 31 11.12 i 2 c specifications table 18 describes the timing requirements for the i 2 c system. the i 2 c module is driven by the periphe ral bus clock (typicall y max 16 mhz) and the scl bit clock is generated from a prescaler. figure 9. i 2 c timing diagram note the i 2 c timing limits reflect values that are necessary meet to the i 2 c bus specification. table 18. i 2 c signal dc specifications (i2c_sda and i2c_scl) parameter symbol min typical max unit input low voltage v il -0.3 - 0.3 v ddint v input high voltage v ih 0.7 vbatt - vbatt + 0.3 v input hysteresis v hys 0.06 vbatt ? v output low voltage 1 (i ol = 5 ma) 1 sda and scl are open drain outputs v ol 0 - 0.2 vbatt v input current (v in = 0 v or v ddint )i in --1a pin capacitance c in <10 pf sda scl t f t hd t low t r t hd;dat t su;dat t high t f ssr t su;sta t hd:sta p t r t buf s t su;sto
mc1323x advance information, rev. 0.0 32 freescale semiconductor 11.13 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power sources other than the normal v dd supply. the flash is 81920 bytes organized as 80 pages by 1024 bytes. flash erase and program may only be executed with cpu cl ock programmed for 32 mhz (default) note flash erase and program may only be executed with cpu clock programmed for 32 mhz (default). fl ash operations are hardware state machine controlled. user code need not count cycles. the following information is supplied for calculati ng approximate time to program and erase. table 19. i 2 c signal ac specifications 1 1 all values referred to v ihmin and v ilmax levels parameter symbol stand ard-mode fast-mode unit min max min max scl clock frequency (when source) f scl 0 100 0 150 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - s low period of the scl clock t low 4.7 - 1.3 - s high period of the scl clock t high 4.0 - 0.6 - s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - s data hold time t shd;dat 0 2 2 a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3.45 3 3 the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 0 2 0.9 3 s data setup time t su:dat 250 - 100 4 4 a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat >= 250 ns must then be met. this will automatically be the case if th e device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard- mode i2c-bus specificatio n) before the scl line is released. -ns rise time for both sda and scl signals t r - 1000 20 + 0.1c b 5 5 c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, the faster fall-times are allowed. 300 ns fall time for both sda and scl signals t f - 300 20 + 0.1c b 5 300 ns bus free time between a stop and start condition t buf 4.7 - 1.3 - s capacitive load for each bus line c b - 400 - 400 pf
mc1323x advance information, rev. 0.0 freescale semiconductor 33 12 applications information note freescale provides a complete suite of design support material including development hardware and software, reference manuals, and hardware references designs for the mc1323x. the applications material presented here is primarily for illustrative purposes. figure 10 illustrates a basic applicati ons circuit based on the 123x-mrb de velopment board. features of the circuit include: ? 32 mhz reference oscillator crystal (y1) is required, and must meet defined specifications ? pulldown resistor on signal pta2 assures that de vices does not enter factory test mode on power-up ? power supply voltage (v_ic) can range from 1.8 vdc to 3.6 vdc (see table 7 for usage notes) ? rf interface circuitry - ? 50/100 (unbal/bal) balun converts device differential, bidirect ional rf port to single-ended 50-ohm antenna port ? control signal rf_bias switches rf reference vol tage to the balun as required for tx or rx ? l1 provides impedance matching for mc1323x rf port ? c4 and l2 network provides a harmonic trap for out-of-band harmonics and spurs on tx ? a low-cost, copper pcb ?f? antenna is s hown. this is a common option, although other antennas such as a chip antenna or antenna module may also be used note ? rf circuitry at 2.4 ghz is very dependent on board layout and component usage. figure 10 shows a typical rf configuration, however component value and use can vary based on customer application. ? mechanical design information fo r the mc1323x package and assembly recommendations can be found in the freescale ieee 802.15.4 / zigbee table 20. flash characteristics characteristic symbol min typical max unit supply voltage for progra m/erase/read operation v batt 1.6 3.6 v byte program time (random location) t prog 40 s per byte program time (burst mode) - excludes start/end overhead t burst 20 s sector erase time t sector 20 ms mass erase time t mass 20.1 ms program/erase endurance t l to t h = ?40 c to + 85 c t = 25 c 20,000 100,000 ? ? cycles data retention @ 25 ct d_ret 100 ? years
mc1323x advance information, rev. 0.0 34 freescale semiconductor package and hardware layout considerations reference manual , doc no. zhdcrm.pdf figure 10. mc13233x basic applications circuit j1 hdr 2x3 1 2 3 4 6 5 32mhz xtal l1 0.0033uh 1 2 rf_bias c1 12pf ant1 f_ant enna z1 50/ 100 ohms 5 1 6 2 3 4 c18 & c26 place close to u1.47 r2 10k extal_32m v_ic bd m c6 10pf dnp c5 10pf l2 0.0039uh 1 2 c2 12pf c4 1pf c3 10 pf u1 mc1323x pta0/xtal_ 32 k 1 pta1/exta l_3 2k 2 reset 3 pta2 4 pta3/irq 5 pta4/xtal_ 32 k_ out 6 pta5/sda 7 pta6/scl 8 pta7/bk gd/ms 9 ptb0/kb i1p 0 10 ptb1/kb i1p 1 11 ptb2/kb i1p 2 12 ptb3/kb i1p 3 13 ptb4/kb i1p 4 14 ptb5/kb i1p 5 15 ptb6/kb i1p 6 16 ptb7/kb i1p 7 17 ptc0/ kbi2p0 18 ptc1/ kbi2p1 20 ptc2/ kbi2p2 21 ptc3/ kbi2p3 22 ptc4/ spic lk 23 ptc5/ ss 24 ptc6/ miso 25 ptc7/ mosi 26 ptd0/tpm0 27 ptd1/tpm1 28 ptd2/tpm2 29 ptd3/tpm3 30 ptd4 /cmt 31 ptd5/ txd 32 ptd6 /rxd 33 ptd7 34 xt a l _ 3 2 m 35 extal_32m 36 rf_p 42 rf_n 41 nc 40 nc/ tinj_n 45 rf_bias/tinj_p 43 pa d 49 vbatt_1 48 vbatt_2 44 vbatt_3 37 vbatt_4 19 vre g_v c o 38 vd d_ an a 39 vre g_lo2 46 vreg_ana 47 xtal_32m exta l_ 3 2m rf_ant rf _50 xt a l _ 3 2 m v_ic z_rf_n c9 0.01uf c15 0.22uf y1 32 mh z 1 4 3 2 v_ic v_i c c8 10uf c7 0. 1u f c14 0.22u f rf _p c8 & c28 place close to u1.39 rf _n harmonic trap c11 8. 2 pf c12 8. 2 pf z_rf_p c10 0.22u f r1 10 k rf _bias c13 0.22uf
mc1323x advance information, rev. 0.0 freescale semiconductor 35 13 mechanical diagrams (case 2124-02, non-jedec) figure 11. mechanical diagram (1 of 2)
mc1323x advance information, rev. 0.0 36 freescale semiconductor figure 12. mechanical diagram (2 of 2)
notes mc1323x advance information, rev. 0.0 freescale semiconductor 37
document number: mc1323x rev. 0.0 05/2011 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale se miconductor assume any liability arising out of the application or use of any product or circuit, and sp ecifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor d oes not convey any lice nse under its patent rights nor the rights of others. freescale semiconduc tor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other ap plications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal inju ry or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semico nductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against a ll claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006, 2007, 2008, 2009, 2010, 2011. all rights reserved.

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